1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a method of forming a void for the purpose of reducing the capacitance between adjacent wires when forming buried wiring patterns in a semiconductor device.
2. Description of Related Art
In recent years, with an increase in the level of integration of semiconductor devices the pitch between wiring conductors in devices has become narrows. When this occurs, the resulting large capacitance between a conductor and adjacent conductors is greatly influenced by changes in potential in an adjacent conductor. This results in reducing the operating margin and leading to the problem of deteriorated performance in the form of misoperation. To solve this problem, there have been methods proposed in the past for providing a void between conductors during the semiconductor manufacturing process. When providing a void between wiring conductors, because of intervening air, which has a small dielectric coefficient, the capacitance between conductors is reduced. An example of the most typical method is that which is disclosed in the Japanese Unexamined Patent Publication (KOKAI) No. 6-5643. That method will be described simply below, with reference being made to FIGS. 3a-3b.
First, as shown in FIG. 3a, an interlayer insulating film 2 is formed on a semiconductor substrate 1, a tungsten plug 4 being formed on a prescribed position with an intervening barrier metal 3 such as titanium or titanium nitride or the like.
Then, an aluminum film or the like is deposited as the wiring metal, and the wiring pattern 5 is formed on this, using conventional photolithography and etching technologies.
Next, as shown in FIG. 3b, an insulation film 6 is deposited by using the conventional CVD method. By using characteristics of the configuration formed by the CVD process, and protrusions and depressions of the wiring pattern 5, a void 7 is formed between the narrow area between wiring conductor parts.
Multilayer wiring technology is commonly used with an increasing level of integration of semiconductor devices. To prevent breaks in an upper portion of the above-noted when forming the upper layer wiring, it is important to smooth any sudden changes in height formed by the wirings.
The use of a so-called buried conductor, which flattens the upper surface by burying the conductor metal within a groove formed in the base insulation layer has been proposed as an effective means to do this. A method of forming a buried conductor is disclosed, for example, in the Japanese Unexamined Patent Publication (KOKAI) No. 58-147045 and the Japanese Unexamined Patent Publication (KOKAI) No. 61-152040. This method will be explained in brief, with reference being made to FIG. 4.
As shown in FIG. 4, after first successively forming an interlayer insulation film 10, a silicon nitride film 11, and a first silicon dioxide film 12 on a semiconductor substrate 9, a groove 13 is formed so as to correspond to the wiring pattern. Next, after successively depositing a barrier metal 14, such as titanium or titanium nitride, and an aluminum film 15 over the entire substrate surface, a method of chemical mechanical polishing (hereinafter referred to as CMP) is used to remove the metal films 14 and 15 from the first silicon dioxide film 12, so as to leave the metal films 14 and 15 only within the groove. Then, the second silicon dioxide film 16 is deposited.
According to this method, it is possible to obtain a flat surface without height irregularities, thereby not only facilitating the formation of an upper pattern with fine features but also preventing breaks in the wiring. Since there is no halation caused by the conductor metal during exposure compared with the wiring formation method of the past, in which the metal conductive film was etched to form the wiring pattern because it is easier to form a fine groove pattern in the insulation film, the formation of a fine wiring pattern is also facilitated.
In addition, according to this method, it is possible to perform self alignment of via-contact holes with the wiring grooves for making contact with the bottom layer electrodes. Further, it is possible to devise a manufacturing method in which the via-contact holes and wiring grooves are filled with metal simultaneously. By doing this, the pattern offset that can occur in the case in which via-contact hole formation and filling are done separately from the wiring pattern formation does not occur.
As described above, with an increase in the level of integration of semiconductor devices, it is desirable to easily use a buried wiring structure for the purpose of facilitating the formation of the upper wiring pattern, and also to provide a void between conductors so as to reduce the capacitance between adjacent conductors.
However, in the above-described previous method of providing a void between conductors, the protrusions and depressions of the wiring pattern and the characteristics of the pattern deposited by using the CVD process are used to form a void between conductors as is clear from FIG. 3b, this does not enable the achievement of a flat surface such as with buried conductors, thereby also making the formation of fine patterns difficult.
In the Japanese Unexamined Patent Publication (KOKAI) No. 1-91435, a method of forming an additional film is disclosed, in which a conductive metal film is deposited first. After a wiring patterns has been formed by utilizing exposure, developing, and etching technologies, an insulating film is deposited over the entire surface thereof. Then exposure, developing, and etching technologies is used to form an additional film of insulating film material in the broad area between wires.
In doing this, after forming a wiring pattern using the etching method of the past, it is possible to provide a void 21 between the narrow area between conductors and achieve a flat surface also by applying the above-described method disclosed in the patent application publication. That is, by forming a projection film 18 having the same thickness of the wiring film 19 and which is provided among the wiring patterns, the pitch thereof being relatively wider than others, as shown in FIG. 5, and then depositing the insulation layer 20 over them.
However, because this method involves the troublesome step of forming an additional film, it does not offer the advantages of the buried conductor method which is a method of forming a wiring pattern, of easy formation of a fine pattern and of the ability to achieve self-alignment of the formation of vias and contact with the wiring pattern.
To solve the above-noted problems, an object of the present invention is to provide a method of manufacturing a semiconductor device which can be used to provide a void formed among these wiring patterns when using the buried conductor method, thereby achieving a reduction of capacitance between adjacent conductors, without sacrificing the advantages of the buried conductor method.